Conceptual Modeling Study

Plasma Heat Recovery via Thermoelectric Stack

A theoretical thermal-systems design exercise exploring whether plasma-adjacent waste heat could be routed through a layered shielding + thermoelectric (TEG) stack to produce electrical output under extreme constraints. Emphasis is on workflow: translating high heat-flux environments into models, running parametric studies, and communicating engineering tradeoffs clearly.

ANSYS Fluent Thermal Stack Modeling Thermoelectrics (TEG) Shielding Trades Parametric Studies

Scope: This is not a validated hardware system. No experimental testing is claimed. The purpose is to demonstrate systems engineering and simulation reasoning under realistic constraints (heat flux, materials limits, interfaces, mass/power trade space).

Objectives & Constraints

Objective
Maximize recoverable power per mass
Primary Constraints
Thermal limits, shielding integrity, interfaces
  • Recover usable ΔT across a TEG layer without overstressing upstream shielding.
  • Maintain protective function (particle/neutron/radiation attenuation as applicable).
  • Bound interface risks (thermal cycling, contact resistance, delamination).
  • Produce a trade map: output vs mass/complexity vs survivability margin.
Assumptions (explicit)
  • Boundary heat fluxes represented as steady and pulsed cases (duty-cycle envelope).
  • Material properties treated as temperature-dependent where available; otherwise bounded ranges.
  • TEG modeled as an effective layer for ΔT and heat flow (electrical performance reported as estimate).
  • Results used for screening/trade direction, not certification or flight/plant design.

Simulation Snapshot (Placeholder)

Drop in: isotherms + heat-flux vectors, ΔT across TEG, and stack comparison chart.
Add figures when you’re ready (even NDA-safe mock plots work).
Suggested figure set (recruiter-friendly)
  • Temperature field through the stack (one representative case).
  • ΔT map across the TEG layer (where power is coming from).
  • Trade plot: output vs stack mass (2–3 design points).

Modeling Workflow

  • Define plasma-side heat flux envelope (steady + pulsed duty cycle cases).
  • Build layered stack model: plasma-facing layer → shielding/moderation → interface → TEG → sink.
  • Solve temperature/gradient fields (steady/transient screening).
  • Extract: peak temperatures, ΔT across TEG, and interface gradients / thermal cycling ranges.
  • Run parametric sweeps (thickness, materials, contact assumptions) to map feasible regions.

Materials & Shielding Stack (Concept Candidates)

Layer Candidate Material(s) Primary Function
Plasma-Facing Surface Graphite / Tungsten Handles particle/radiation load path; high-T survivability and erosion resistance.
Shielding / Buffer BeO + Graphite (stack) Attenuation/moderation (as applicable) and thermal buffering to protect downstream layers.
Thermoelectric Layer Bi₂Te₃ TEG Array (screening candidate) Converts heat-flow-driven ΔT into electrical output; electrical isolation considered.
Risks & Mitigations (concept-level)
  • Thermal cycling / fatigue: evaluate transient envelopes; design margins; compliant interlayers.
  • Interface contact resistance: sensitivity sweep; bounded cases; prioritize robust interfaces.
  • Radiation/particle damage: keep TEG protected behind shielding; treat properties as degraded bounds.
  • Mass/power realism: report “screening estimates” with assumptions, not point claims.
Last updated: October 2025 • Status: Concept / Modeling Study